An Efficient VLSI Computation Reduction Scheme in H.264/AVC Motion Estimation

The variable block sizes motion estimation in H.264 is key technique to remove inter-frame redundancy. This technique not only requires huge memory bandwidth but also its computation complexity is higher. Therefore, this paper proposes one efficient sub-pixel search algorithm for reducing computation complexity and bandwidth utilization, and a novel VLSI architecture for this algorithm which simplifies variable block sizes motion estimation. The proposed method is efficient compared with those of existing methods which have negative effects on compression, with respect to chip area, operation frequency, and throughput rate. The proposed sub-pixel search architecture decreases the numbers of search pixels of full pixels motion estimation by around 70% and the chip area by around 40% than the others search algorithm. Besides, an optimized motion estimation MV prediction algorithm is used to remove data dependency, and optimization storage policies are used to save hardware resources. The proposed sub-pixel search architecture can work at 200 MHz with 530k gate count, which supports high-definition television 1920×1080 format. Key-Words: sub-pixel search, systolic array, H.264 encoder, motion estimation, 1080P, HDTV, VLSI